As integrated circuits increase in density and complexity and are required to meet more stringent, diverse, and higher-speed input/output (I/O) interface standards, clock and data timing management becomes an important design consideration. Typically, a phase-locked loop (PLL) or a delay-locked loop (DLL) is employed to provide clock management and attempt to minimize timing issues such as clock skew, clock delay, and clock jitter.
In general, the PLL monitors and locks onto a reference signal, such as a system clock, to manage or synthesize various clock signals. The DLL also monitors and locks onto a reference signal (e.g., a system clock), but utilizes a delay line rather than a voltage controlled oscillator, to manage and provide the clock management function. A drawback of these types of systems is that the PLL and DLL methods often involve the generation of numerous clock signals and routing structures (e.g., a PLL or a DLL and associated clock distribution network for each type of I/O interface standard being supported), which is inefficient and consumes valuable circuit area and may result in difficult layout constraints. As a result, there is a need for an improved technique for managing clock and data timing relationships.